The present invention relates generally to methods for forming integrated circuit chips, and more particularly, to a method for substantially eliminating tunnel oxide thinning and weak oxide problems resulting from the trench-forming isolation process.
An integrated circuit chip comprises an array of devices formed in a semiconductor substrate, with the contacts for these devices interconnected by patterns of conductive wires. These devices must be isolated from each other in order to properly function. One method used in the art to isolate CMOS circuits is the use of isolation trenches with vertical sidewalls. Such isolation trenches are advantageous in that they have a significantly smaller width than standard LOCOS isolation field oxide regions of the same depth. However, it has been discovered that the dry etching techniques utilized to form the deep isolation trenches tend to damage the silicon at the top of the mesas of silicon bordering the isolation trench. Specifically, the plasma molecules bombarding the silicon damage the silicon lattice resulting in a rough surface. In succeeding steps when tunnel oxide is grown on top of the silicon mesas, the oxide quality at the damaged edges of the mesas is thin and relatively weak. If the gate region for transistors is formed in the damaged silicon below these weak oxide areas, then there is a high potential for shorting of the gate through the oxide. This is a particular problem for floating gate structures formed in integrated circuits. Such floating gate structures receive data by means of electron tunnelling across a tunnel oxide up to the gate. It has been discovered that if a corner of the tunnel oxide contains defect sites caused by a damaged silicon layer thereunder, then electrons can leak back out of the gate through these defect sites, thereby losing the data on the gate and causing data retention problems. Additionally, if substantial electron tunneling occurs at the location of the thin oxide at a corner (which would tend to occur since the thinness of the corner makes that location the path of least resistance), then a tunnel oxide breakdown and short at that point can occur. This presents a significant reliability problem for chips utilizing such an isolation process.